It seems that today, the most compelling desire in the computer industry is the desire for improved performance. Engineers and designers are continually attempting to extract the most speed from each component in a computer system. One computer component which receives much attention by computer system designers is random access memory (RAM) chips. RAM chips are used within a computer system as volatile information storage while the computer is processing. Information is stored in the RAM chips using a matrix-type addressing scheme. A unique hexadecimal address is associated with each storage location on the RAM chip.
To access the information, another computer component, such as a central processing unit (CPU), provides to a RAM chip an address for the desired information and an indication that the information will be read from or written to the RAM chip. Often, large blocks of contiguous information are read from or written to a RAM chip in sequential order. For instance, the CPU may read four contiguous 64-bit words or blocks of information (a "sequential data transfer") from the RAM chip. In the traditional manner, the CPU performs four separate memory accesses to read each of the four blocks of information. Each memory access would include providing the RAM chip with an address for the current block of information, and then issuing a read command. The step of providing to the RAM chip the addresses for each successive block of information in the sequential data transfer creates a performance limitation. The need for the requesting component, the CPU in this example, to provide each successive address slows the overall data access for such a sequential data transfer.
Burst-mode data transfer is one attempt to improve the performance of memory access during a sequential data transfer. To enable a burst-mode data transfer, the RAM chip is modified to include a burst-mode address counter or "incrementer" (the "burst counter"). The purpose of the burst counter is to internally increment the address of the current data transfer so that the requesting component need not provide each sequential address. The burst counter allows another computer component, such as the CPU, to merely provide to the RAM chip the starting address for the burst transfer and an instruction to perform a burst transfer. The RAM chip begins providing to the CPU the information at the starting address, and the burst counter internally generates the addresses for each successive memory location in the sequential data transfer. The burst counter increments the current address to the next successive address at each clock cycle. Those skilled in the art will appreciate that the burst counter may be configured to operate in an "interleave" mode in which the address generated by the burst counter may not necessarily be the next successive address. However, for simplicity, the following discussion will focus on the generation of successive addresses. Those skilled in the art will appreciate that the invention is equally applicable to interleaved addressing. Burst-mode enabled RAM chips greatly improve the overall performance of a computer system by reducing the overhead associated with accessing sequential information stored on the RAM chip.
To perform most efficiently, the RAM chip should be capable of providing each successive address location in the burst transfer as quickly as possible. Toward that end, the burst counter should be capable of providing the RAM chip with the second sequential address in the burst transfer as early as possible. The RAM chip may need the second of the sequential addresses as early as the end of the initial clock cycle. Existing technologies for generating sequential addresses fall short of an ideal solution. For instance, one attempt to provide the second of the sequential addresses is to use an incrementer between the externally provided initial address and the latches of the burst counter. In that manner, the initial address is incremented prior to being loaded into the burst counter. However, that solution is costly in terms of the surface area needed for additional components on the RAM chip, i.e., the additional incrementer. Another solution is to load the initial address into the burst counter in the first clock cycle, and then increment the burst counter with the second clock cycle. That solution is costly in terms of the performance loss of not having the second sequential address by the end of the first clock cycle.
Accordingly, there is a need in the art for a circuit to control the load and increment of the latches of a burst counter on a burst-mode capable RAM chip which is capable of both loading an initial address and incrementing that initial address within the first clock cycle.